A common serial communication interface known as Inter-Integrated Circuit bus (I2C) utilizes two wires for data transfer: a serial data (SDA) line for serial transmission of data and a serial clock (SCL) line for the transmission of a clock signal. With reference to FIG. 1, the SDA 14 and the SCL 16 lines originate from a master device 10 such as a microcontroller. One or more slave devices 12, such as an RF serial interface, could be connected to the master device 10 through the SDA line 14 and the SCL line 16. Each communication session must be initiated by the master device 10, which also controls the clock signal on the SCL line 16. Each slave device 12 comes with a predefined device address, the lower bits of which may be configurable at a board level. The master device 10 transmits a device address of the intended slave at the beginning of every transaction. Each slave device 12 is responsible for monitoring the SDA line 14 and responds only to its own address. The master device 10 begins the communication by issuing a start condition. The master device 10 then sends a unique 7-bit slave device address, with the most significant bit first. The eighth bit after the start condition specifies whether the slave device 12 is to receive (“0”) or to transmit (“1”). Upon receipt and recognition of the slave device 12 address, the addressed slave device 12 sends an ACK bit on the SDA line 14 to signify that it is ready to receive or to transmit. Then the transmitter (slave device 12 or master device 10, as indicated by the content of the ACK bit) transmits a byte of data starting with the most significant bit. After receiving the data byte, the receiver issues a new ACK bit. This 9-bit pattern is repeated if more bytes need to be transmitted.
In a write transaction (slave device 12 receiving), when the master device 10 is done transmitting all of the data bytes it wants to send, it monitors for a last ACK signal and then issues a stop condition on the SDA line 14. In a read transaction (slave device 12 transmitting), the master device 10 does not acknowledge the final byte it receives. Instead, it issues a stop condition, indicating that it has received all the information it asked for.
Another common option for low-cost, low speed communication is a serial peripheral interface (SPI). SPI specifies four signals: clock (SCLK), master data output/slave data input (MOSI), master data input/slave data output (MISO), and slave select (CSS). Similar to I2C, SPI devices communicate using a master-slave relationship. FIG. 2 shows these four signals in a single-slave configuration. In the figure, an SPI master device 20 is connected to one or more slave devices 22 through four lines carrying the MOSI signal 24, the MISO signal 26, the SCLK signal 28, and the CSS signal 30. The SCLK signal 28 and the CSS signal 30 are generated by the master device 20 and are provided to all connected slave devices 22. Each additional slave device shares the same MOSI signal line 24, MISO signal line 26, and SCLK signal line 28 but each slave device has its own dedicated CSS signal line 30 connected the master device 20.
The MOSI signal line 24 carries data from the master device 20 to the slave device 22. The MISO signal line 26 carries data from the slave device 22 back to the master device 20. A slave device 22 is selected when the master device 20 asserts the particular CSS signal line 30 that is connected to a particular slave device 22. With two data lines, one for each traffic direction, SPI allows full duplex data transmission. Once the master device 20 generates a clock signal and selects a slave device 22, data may be transferred in both directions simultaneously. In fact, as far as SPI is concerned, data are always transferred in both directions. It is up to the master 20 and slave devices 22 to know whether a received byte is meaningful or not.
With an ability to stream data (as opposed to reading and writing addressed locations in a slave device), an SPI system provides a high data transfer rate. However, the SPI does not have an acknowledgement mechanism to confirm receipt of data, nor does it offer any flow control. Without a communication protocol, the SPI master has no knowledge of whether a slave even exists.
A limitation common to both the I2C interface and the SPI interface is that the communicating devices must be configured into a master/slave relationship, which means that the master is the only device that can initiate a communication session. Furthermore, without any acknowledgment mechanism, the SPI has no way to prevent buffer overflows in the receiving device. In the case of I2C, though an acknowledge bit is sent by the receiver each time a byte is received, the acknowledge bit has to be sent through the data line. As a result, the rate of data transfer is reduced. Therefore, it would be desirable to have an interfacing system that allows either of the communicating devices to initiate a communication session. It would also be desirable to have an interfacing system that provides a buffer overflow protection mechanism that does not take up communication bandwidth.